Guard Rings including Semiconductor Fins and Regrown Regions

ABSTRACT

A method includes forming a gate stack over a semiconductor fin, wherein the semiconductor fin forms a ring, and etching a portion of the semiconductor fin not covered by the gate stack to form a recess. The method further includes performing an epitaxy to grow an epitaxy semiconductor region from the recess, forming a first contact plug overlying and electrically coupled to the epitaxy semiconductor region, and forming a second contact plug, wherein the second contact plug is overlying and electrically coupled to the gate stack.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No.14/719,586, entitled “Methods for Forming Guard Rings on FinStructures,” filed May 22, 2015, which application is a divisional ofU.S. patent application Ser. No. 14/166,510, entitled “Methods forForming Guard Rings on Fin Structures,” filed Jan. 28, 2014, now U.S.Pat. No. 9,053,947, issued Jun. 9, 2015, which application is adivisional of U.S. patent application Ser. No. 13/644,261, entitled“Guard Rings on Fin Structures,” filed on Oct. 4, 2012, now U.S. Pat.No. 8,723,225, issued May 13, 2014, which applications are incorporatedherein by reference.

BACKGROUND

Guard rings are formed in integrated circuits as isolation regions ofdevices. Conventional guard rings may include semiconductor regionssurrounding the circuit devices. The guard rings may be connected topower supply voltages VDD, or may be grounded.

In the integrated circuits that adopt Fin Field-Effect Transistors(FinFETs), the guard rings may also adopt fin shapes. For example, theformation of some guard rings includes etching silicon fins to formrecesses, and epitaxially growing silicon germanium in the recesses. Thegrown silicon germanium forms the guard ring. Since the guard rings aretypically long, non-uniformity occurs in the growth of silicongermanium. As a result, some portions of the grown silicon germanium mayhave thicknesses significantly smaller than other portions. Furthermore,the surfaces of the grown silicon germanium may be rough. This resultsin a high resistance in the grown silicon germanium and poor landing ofcontact plugs.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantagesthereof, reference is now made to the following descriptions taken inconjunction with the accompanying drawings, in which:

FIGS. 1A through 6A are cross-sectional views and a top view ofintermediate stages in the manufacturing of a guard ring in accordancewith some exemplary embodiments;

FIGS. 6B and 6C are cross-sectional views of the structure in FIG. 6A;and

FIG. 7 illustrates an exemplary guard ring in accordance with exemplaryembodiments, wherein the structure in FIGS. 6A-6C is a part of the guardring.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments of the disclosure are discussedin detail below. It should be appreciated, however, that the embodimentsprovide many applicable inventive concepts that can be embodied in awide variety of specific contexts. The specific embodiments discussedare illustrative, and do not limit the scope of the disclosure.

A guard ring and the method of forming the same are provided inaccordance with various exemplary embodiments. The intermediate stagesof forming the guard ring are illustrated. The variations and theoperation of the embodiments are discussed. Throughout the various viewsand illustrative embodiments, like reference numbers are used todesignate like elements.

Referring to FIG. 1A, an integrated circuit structure is formed. Theintegrated circuit structure includes substrate 20, which may be a bulksemiconductor substrate or a Semiconductor-on-Insulator (SOI) substrate.Substrate 20 may be lightly doped with a p-type or an n-type impurity.Isolation regions such as Shallow Trench Isolation (STI) regions 22 maybe formed in substrate 20, and may extend from the top surface ofsubstrate 20 into substrate 20. Fins 24 are formed over the top surfacesof STI regions 22. Fin 24 may be formed by removing top portions of STIregions 22, so that the portions of semiconductor material betweenneighboring STI regions 22 becomes fins 24. FIG. 1A also illustratessemiconductor strips 25 between STI regions 22. Semiconductor strips 25and fins 24 may be formed of a same semiconductor material such assilicon. Furthermore, semiconductor strips 25 may a portion of substrate20, and may be formed of a same material as the bulk substrate portionof substrate 20, which bulk substrate portion is underlying STI regions22. In some embodiments, each of semiconductor strips 25 and fins 24forms a ring, as shown in FIG. 1B.

Referring to FIG. 2, a plurality of gate stacks are formed, eachincluding one of gate dielectrics 26 and one of gate electrodes 28. Gatedielectrics 26, which may be formed of silicon oxide, silicon nitride,silicon oxynitride, a high-k dielectric material, or the like, areformed on the top surfaces and sidewalls of fin 24. Gate electrodes 28are formed over gate dielectrics 26. Gate electrodes 28 may be formed ofa conductive material such as polysilicon, a metal, a metal alloy, ametal silicide, or the like. In the embodiments wherein gate electrodes28 are formed of polysilicon, hard masks such as silicon nitride layersmay be formed over each of gate electrodes 28. Although not illustratedin FIG. 2, gate spacers 29, which are shown in FIGS. 6B and 6C, are alsoformed on the opposite sidewalls of gate electrodes 28. In someembodiments, distances D1 between neighboring gate electrodes 28 aresmaller than about 0.2 μm, and may be between about 0.05 μm and about0.2 μm, although a greater or a smaller distance may be used. It isappreciated, however, that the dimensions recited throughout thedescription are merely examples, and may be changed to different values.

Only three gate stacks are illustrated in the illustrated embodimentsfor clarity. In the embodiments, however, there may actually be manygate stacks distributed throughout the semiconductor ring of fin 24,which gate stacks are shown in FIG. 7. The distances D1 betweenneighboring gate stacks are also controlled not to exceed the desirablerange.

Referring to FIG. 3, the exposed portions of fins 24 not covered by gatedielectrics 26, gate electrodes 28, and gate spacers 29 (FIGS. 6B and6C) are removed (recessed), while the covered portions of fins 24 arenot removed. The removal may be performed through a dry etch step. Thespaces left by the removed portions of fins 24 are referred to asrecesses 30 hereinafter. Recesses 30 may have bottoms lower than the topsurfaces of STI regions 22. As a result, portions of semiconductorstrips 25 are also removed, and the top surfaces of the remainingsemiconductor strips 25 are exposed. In alternative embodiments, thebottoms of recesses 30 are lower than the top surfaces of STI regions22.

Next, as shown in FIG. 4, epitaxy semiconductor regions 36 are grownfrom recesses 30 in FIG. 3 through epitaxy. Epitaxy semiconductorregions 36 have a lattice constant different from the lattice constantof fins 24 (FIG. 1) and/or the lattice constant of semiconductor strips25. In some embodiments, epitaxy semiconductor regions 36 comprisesilicon germanium (SiGe). In alternative embodiments, epitaxysemiconductor regions 36 comprise silicon carbon (SiC). Epitaxysemiconductor regions 36 may be formed using one of Chemical VaporDeposition (CVD) methods. The precursors for forminggermanium-containing epitaxy semiconductor regions 36 may includeSi-containing gases and Ge-containing gases, such as SiH₄ and GeH₄,respectively, and the partial pressures of the Si-containing gases andGe-containing gases are adjusted to modify the atomic ratio of germaniumto silicon. In some embodiments, the atomic percentage of germanium inepitaxy semiconductor regions 36 is greater than about 20 atomicpercent. Alternatively, epitaxy semiconductor regions 36 comprise SiC,with the atomic percentage of carbon being greater than three percent,for example. Epitaxy semiconductor regions 36 may form a guard ringalong with fins 24 in accordance with embodiments. The guard ring formedof semiconductor regions 36 and fins 24 may be a full ring, with nobreak therein in accordance with some embodiments.

During the epitaxy for forming epitaxy semiconductor regions 36, p-typeimpurities such as boron or n-type impurities such as phosphorous may bedoped with the proceeding of the epitaxy. For example, when epitaxysemiconductor regions 36 comprise SiGe, p-type impurities are doped.Otherwise, when epitaxy semiconductor regions 36 comprise SiC, n-typeimpurities are doped. The impurity concentration of the p-type or n-typeimpurity may be between about 1×10¹⁹/cm³ and about 1×10²¹/cm³. Inalternative embodiments, no p-type and n-type impurity is in-situ doped.Instead, the impurities are doped into epitaxy semiconductor regions 36through implantation after their formation.

Due to different growth rates on different surface planes, the growth ofepitaxy semiconductor regions 36 comprises lateral growth and verticalgrowth. Facets are hence formed as being the surfaces of epitaxysemiconductor regions 36, as shown in FIG. 4. The epitaxy semiconductorregions 36 grown from neighboring recesses may be merged with each otherto form a large epitaxy region.

After the formation of epitaxy semiconductor regions 36, silicideregions 38 (not shown in FIG. 4, refer to FIGS. 6B and 6C) may be formedon the top surfaces of epitaxy semiconductor regions 36. Next, referringto FIG. 5, metal contact plugs 40 are formed over and electricallyconnected to epitaxy semiconductor regions 36. Metal contact plugs 40may be overlying and in contact with silicide regions 38, as shown inFIGS. 6B and 6C. Metal plugs 40 may have a longitudinal direction (theillustrated X direction in FIG. 5) perpendicular to the longitudinaldirection (the illustrated Y direction) of original fins 24 (as in FIG.1). Furthermore, metal contact plugs 40 may also include portionslanding on STI regions 22.

In some embodiments, gate electrodes 28 are left in the final Guardring. In alternative embodiments, gate electrodes 28 may be removed, andreplaced by metal gates, which metal gates are referred to asreplacement gates. The process for forming the replacement gates mayinclude forming a first Inter-Layer Dielectric (ILD) 42 (not shown inFIG. 5, shown in FIGS. 6B and 6C), removing gate electrodes 28 and theoverlying hard masks (if any) to form recesses, depositing a metal tofill the resulting recesses left by the removed gate electrodes 28, andpolishing the metal to form the replacement gates. Throughout thedescription, the replacement gates, if any, are also referred to as gateelectrodes 28.

FIG. 6A illustrates the formation of contact plugs 44 over andelectrically connected to gate electrodes 28. FIGS. 6B and 6C illustratecross-sectional views of the structure in FIG. 6A, wherein thecross-sectional views are obtained from the vertical plane crossinglines 6B-6B and 6C-6C, respectively, in FIG. 6A. FIG. 6B illustrates theplane that crosses the remaining portions of semiconductor strips 25,wherein epitaxy semiconductor regions 36 are formed over and contactingsemiconductor strips 25. The bottom surface of STI regions 22 (not inthe plane of FIG. 6B, refer to FIGS. 6A and 6C) is marked as 22A.Contact plugs 40 are over and electrically connected to epitaxysemiconductor regions 36, and may be further connected to metal line 46.Metal line 46 may also be electrically coupled to gate electrodes 28through gate contact plugs 44, which is illustrated using dashed linessince they are not in the plane of FIG. 6B. During the operation of theintegrated circuits, voltage VGR is applied to metal line 46.Accordingly, epitaxy semiconductor regions 36 and gate electrodes 28 areapplied with the same voltage VGR, which is generated by voltage source48.

In some embodiments, epitaxy semiconductor regions 36 are doped with ap-type impurity, and may comprise silicon germanium. Accordingly,voltage VGR may be a negative voltage. Alternatively, voltage VGR isequal to VSS. Accordingly, holes are attracted to, and accumulated inregions 50, which are overlapped by, and contacting, gate dielectrics26. Accordingly, regions 50 become p-type channels, in which holes(represented by arrows 53) may flow through. The regions underlying gateelectrodes 28 are accordingly connected to voltage VGR, and hence formsa part of the resulting guard ring, as shown in FIG. 7. Furthermore,through p-type channels 50 in fins 24, the plurality of p-type epitaxysemiconductor regions 36 are interconnected to form a continuous guardring. In these embodiments, well region 52 is formed as a p-well region,in which p-type epitaxy semiconductor regions 36 are located. P-typeepitaxy semiconductor regions 36 are further in contact with p-wellregion 52, so that voltage VGR is also applied to p-well region 52.

In alternative embodiments, epitaxy semiconductor regions 36 are dopedwith an n-type impurity, and may comprise silicon carbon. Accordingly,voltage VGR may be a positive voltage, which may be power supply voltageVDD. Electrons are attracted to and accumulated in regions 50, which areoverlapped by, and in contact with, gate dielectrics 26. Regions 50become n-type channels, in which electrons (represented by arrows 53)may flow through. Therefore, the regions underlying gate electrodes 28are also connected to voltage VGR, and hence forms a part of theresulting guard ring. Furthermore, through n-type channels 50 in fins24, the plurality of n-type epitaxy semiconductor regions 36 areinterconnected to form a continuous guard ring. In these embodiments,well region 52 is formed as an n-well region, in which n-type epitaxysemiconductor regions 36 are located. N-type epitaxy semiconductorregions 36 are further in contact with n-well region 52, so that voltageVGR may be applied to n-well region 52.

FIG. 6C illustrates that gate electrodes 28 and contact plugs 40 alsooverlap STI regions 22. Although gate dielectrics 26 are illustrated asextending between gate electrodes 28 and STI regions 22, gatedielectrics 26 may also not extend to the illustrated plane inalternative embodiments. The illustrated epitaxy semiconductor regions36 are thin in the illustrated plane since they are formed by thelateral growth. As shown in FIG. 6C, voltage VGR may be applied on aplurality of gate electrodes 28 and a plurality of metal contacts 40,which are interconnected through metal line 46.

FIG. 7 illustrates a top view of guard ring 54 in accordance withembodiments. The structure shown in FIG. 6A may be reproduced to includefour portions that form the four sides of guard ring 54. As shown inFIG. 7, a plurality of contact plugs 40 is over and electrically coupledto epitaxy semiconductor regions 36, and a plurality of contact plugs 44is over and electrically couple to gate electrodes 28. In someembodiments, all of gate electrodes 28 of guard ring 54 areinterconnected, and/or applied with the same voltage. All of contactplugs 40 may be interconnected, and/or applied with the same voltage.Furthermore, all of gate electrodes 28 may be connected to all ofcontact plugs 40, and/or applied with the same voltage. Fins 24 (FIG.6A) and epitaxy semiconductor regions 36 are interconnected to form oneor a plurality of semiconductor rings, wherein fins 24 and epitaxysemiconductor regions 36 are allocated in an alternating pattern. Theplurality of semiconductor rings may be full rings, although they mayhave breaks therein.

Guard ring 54 may encircle a region, which region may have a rectangulartop-view shape or any other applicable shape. MOS devices 56 are formedin the region encircled by guard ring 54. In some embodiments, MOSdevices 56 are FinFETs. Accordingly, the fins, the gate dielectrics, thegate electrodes, the source and the drain regions, and the like, of MOSdevices 56 may be formed simultaneously when fins 24 (FIG. 1A), gatedielectrics 26 (FIG. 6A), gate electrodes 28, and epitaxy regions 36,respectively, are formed.

In the embodiments, by forming gate dielectrics 26 (FIG. 6A), gateelectrodes 28, and gate spacers 29 to cover portions of fins 24 beforethe etching of fins 24 and the epitaxy of epitaxy semiconductor regions36, the length D1 (FIG. 2) of each of discrete epitaxy semiconductorregions 36 is reduced. The growth of epitaxy semiconductor regions 36thus has a better uniformity. This in turn results in the reduction inthe non-uniformity of the guard ring and the reduction in the contactresistance of the guard ring.

In accordance with embodiments, a device includes a semiconductorsubstrate, isolation regions extending into the semiconductor substrate,a plurality of semiconductor fins higher than top surfaces of theisolation regions, and a plurality of gate stacks. Each of the gatestacks includes a gate dielectric on a top surface and sidewalls of oneof the plurality of semiconductor fin, and a gate electrode over thegate dielectric. The device further includes a plurality ofsemiconductor regions, each disposed between and contacting twoneighboring ones of the plurality of semiconductor fins. The devicefurther includes a plurality of contact plugs, each overlying andelectrically coupled to one of the plurality of semiconductor regions.An electrical connection electrically interconnects the plurality ofsemiconductor regions and the gate electrodes of the plurality of gatestacks.

In accordance with other embodiments, a device includes a semiconductorsubstrate, isolation regions extending into the semiconductor substrate,and a semiconductor ring encircling a portion of the semiconductorsubstrate. The semiconductor ring includes a plurality of semiconductorfins higher than a top surface of the isolation regions, and a pluralityof epitaxy semiconductor regions contacting the plurality ofsemiconductor fins. The plurality of epitaxy semiconductor regions andthe plurality of semiconductor fins are allocated in an alternatingpattern. The device further includes a plurality of gate dielectrics,each on a top surface and sidewalls of one of the plurality ofsemiconductor fins, and a plurality of gate electrodes, each overlyingone of the plurality of gate dielectrics. A plurality of contact plugsis formed, with each being overlying and electrically coupled to one ofthe plurality of epitaxy semiconductor regions.

In accordance with yet other embodiments, a method includes forming agate stack over a semiconductor fin, wherein the semiconductor fin formsa ring. A portion of the semiconductor fin not covered by the gate stackis etched to form a recess. The method further includes performing anepitaxy to grow an epitaxy semiconductor region from the recess, forminga first contact plug overlying and electrically coupled to the epitaxysemiconductor region, and forming a second contact plug overlying andelectrically coupled to the gate stack.

Although the embodiments and their advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the embodiments as defined by the appended claims. Moreover,the scope of the present application is not intended to be limited tothe particular embodiments of the process, machine, manufacture, andcomposition of matter, means, methods and steps described in thespecification. As one of ordinary skill in the art will readilyappreciate from the disclosure, processes, machines, manufacture,compositions of matter, means, methods, or steps, presently existing orlater to be developed, that perform substantially the same function orachieve substantially the same result as the corresponding embodimentsdescribed herein may be utilized according to the disclosure.Accordingly, the appended claims are intended to include within theirscope such processes, machines, manufacture, compositions of matter,means, methods, or steps. In addition, each claim constitutes a separateembodiment, and the combination of various claims and embodiments arewithin the scope of the disclosure.

What is claimed is:
 1. A device comprising: a plurality of semiconductorfins; a plurality of gate stacks, each comprising: a gate dielectric ona top surface and sidewalls of one of the plurality of semiconductorfins; and a gate electrode over the gate dielectric; and a plurality ofsemiconductor regions, each disposed between and contacting twoneighboring ones of the plurality of semiconductor fins, wherein thegate electrodes of the plurality of gate stacks and the plurality ofsemiconductor regions are electrically shorted with each other.
 2. Thedevice of claim 1, wherein the plurality of semiconductor regions andthe plurality of semiconductor fins are located at a same level, and areconnected together to form a continuous semiconductor ring.
 3. Thedevice of claim 1 further comprising: a semiconductor substrate, whereinthe plurality of semiconductor fins is over the semiconductor substrate;and a well region in the semiconductor substrate, wherein the pluralityof semiconductor regions has a same conductivity type as, and is incontact with, the well region.
 4. The device of claim 1, wherein thegate electrodes of the plurality of gate stacks and the plurality ofsemiconductor regions are electrically shorted through a metal line. 5.The device of claim 1 further comprising a voltage source electricallycoupling to, and configured to apply a same voltage to, the plurality ofsemiconductor regions and the gate electrodes of the plurality of gatestacks.
 6. The device of claim 5, wherein the plurality of semiconductorregions comprises p-type regions, and wherein the voltage source isconfigured to apply a negative voltage to the plurality of semiconductorregions and the gate electrodes of the plurality of gate stacks.
 7. Thedevice of claim 5, wherein the plurality of semiconductor regionscomprises n-type regions, and wherein the voltage source is configuredto apply a positive voltage to the plurality of semiconductor regionsand the gate electrodes of the plurality of gate stacks.
 8. The deviceof claim 1 further comprising: a plurality of contact plugs, eachoverlying and electrically coupling to one of the plurality ofsemiconductor regions; and an electrical connection electricallyinterconnecting the plurality of semiconductor regions and the gateelectrodes of the plurality of gate stacks.
 9. The device of claim 1further comprising: a semiconductor substrate; and isolation regionsextending into the semiconductor substrate, wherein the plurality ofsemiconductor fins is higher than top surfaces of the isolation regions.10. A device comprising: a semiconductor substrate; isolation regionsextending into the semiconductor substrate; a semiconductor ringcomprising: a plurality of semiconductor fins higher than top surfacesof the isolation regions, wherein the plurality of semiconductor fins isformed of a first semiconductor material; and a plurality ofsemiconductor regions interconnecting neighboring ones of the pluralityof semiconductor fins with each other, wherein the plurality ofsemiconductor regions is formed of a second semiconductor materialdifferent from the first semiconductor material; a plurality of gatedielectrics, each on a top surface and sidewalls of one of the pluralityof semiconductor fins; a plurality of gate electrodes, each overlyingone of the plurality of gate dielectrics; and a plurality of contactplugs, each overlying and electrically coupling to one of the pluralityof semiconductor regions.
 11. The device of claim 10, wherein theplurality of contact plugs is electrically shorted to each other. 12.The device of claim 10, wherein the plurality of gate electrodescomprises a gate electrode, with two of the plurality of contact plugsbeing located on opposite sides of the gate electrode, and the devicefurther comprises: a gate contact plug over and contacting the gateelectrode; and a common metal line having a bottom surface in contactwith a top surface of the gate contact plug and top surfaces of the twoof the plurality of contact plugs.
 13. The device of claim 10 furthercomprising a Fin Field-Effect Transistor (FinFET) encircled by thesemiconductor ring.
 14. The device of claim 10, wherein the plurality ofsemiconductor fins comprises silicon fins, and the plurality ofsemiconductor regions comprises silicon germanium or silicon carbon. 15.A device comprising: a semiconductor substrate; isolation regionsextending into the semiconductor substrate; a semiconductor ring withportions higher than top surfaces of the isolation regions; a pluralityof gate dielectrics disposed over the semiconductor ring and spacedapart from each other; a plurality of gate electrodes, each overlyingone of the plurality of gate dielectrics; and a plurality of gatespacers, wherein the plurality of gate electrodes, the plurality of gatedielectrics, and the plurality of gate spacers overlap first portions ofthe semiconductor ring, and the semiconductor ring further comprisessecond portions having top portions, with sidewalls of the top portionsbeing in contact with outer edges of the gate spacers.
 16. The device ofclaim 15, wherein the first portions and the second portions of thesemiconductor ring are formed of different materials.
 17. The device ofclaim 16, wherein the second portions of the semiconductor ring areformed of silicon germanium or silicon carbon, and the first portions ofthe semiconductor ring are formed of silicon.
 18. The device of claim16, wherein the first portions of the semiconductor ring havesubstantially vertical sidewalls, and the second portions of thesemiconductor ring comprise facets.
 19. The device of claim 16 furthercomprising a plurality of contact plugs, each over and electricallycoupled to one of the second portions of the semiconductor ring, whereinthe plurality of contact plugs and the plurality of gate electrodes areelectrically shorted.
 20. The device of claim 15, wherein portions ofthe semiconductor ring between neighboring portions of the plurality ofgate dielectrics extend into regions between the isolation regions tocontact the semiconductor substrate.